# Performance Monitoring Events for Intel(R) Core(TM) processors based on Lunar Lake performance hybrid architecture - V1.18
# 08/05/2025 EVENT_STATUS Legend: None = 0x00, Deprecated = 0x01, Template = 0x02
# Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.
UNIT	CODE	UMASK	UMASK_EXT	NAME	DESCRIPTION	COUNTER	EVENT_STATUS	COUNTER_TYPE
iMC	0x22	0x00	0x00	UNC_M_CAS_COUNT_RD	Read CAS command sent to DRAM	0,1,2,3,4	0x00	PGMABLE
iMC	0x23	0x00	0x00	UNC_M_CAS_COUNT_WR	Write CAS command sent to DRAM	0,1,2,3,4	0x00	PGMABLE
iMC	0x3C	0x00	0x00	UNC_M_TOTAL_DATA	Total number of read and write byte transfers to/from DRAM, in 32B chunk, per DDR channel. Counter increments by 1 after sending  or receiving 32B chunk data.	0,1,2,3,4	0x00	PGMABLE
